Logo Synopsys

ASIC Digital Design Verification Principal Engineer

Job

  • Level
    Senior
  • Job Feld
    Embedded
  • Anstellung
    Vollzeit
  • Vertragsart
    Unbefristetes Dienstverhältnis
  • Ort
    München
  • Arbeitsmodell
    Onsite
  • Job Zusammenfassung

    In dieser Position entwickelst du Verifikationsumgebungen für Interface IP-Protokolle, führst detaillierte Testpläne durch und mentorierst Junior Ingenieure in der Verifizierung mittels System Verilog und UVM.

    Job Technologien

    Deine Rolle im Team

    • Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
    • Collaborating with design and architecture teams to identify and fix bugs.
    • Performing all tasks related to verifying a complex digital IP including detailed test plans, functional coverage analysis and driving coverage closure.
    • Mentoring and guiding junior verification engineers in best practices and methodologies.
    • Conducting design and verification reviews and providing constructive feedback to improve overall quality and functionality.
    • Documenting design specifications, test plans, and verification reports.
    • Proficiency in System Verilog, UVM, SVA, and other verification techniques.
    • Strong understanding of digital design and verification concepts.
    • Excellent problem-solving skills and attention to detail.

    Unsere Erwartungen an dich

    Qualifikationen

    • Proficiency in digital design and verification methodologies.
    • Expertise in using advanced verification techniques.
    • Familiarity with scripting languages such as Python or Perl for automation.
    • Detail-oriented with a strong analytical mindset.
    • Excellent communicator, able to convey complex technical concepts clearly.
    • Collaborative team player who thrives in a dynamic environment.
    • Proactive and self-motivated, with a commitment to continuous learning.
    • A results-driven professional committed to delivering high-quality work.
    • Mentor and leader, capable of guiding and developing junior engineers.

    Erfahrung

    • Experience with developing testbenches using System Verilog and UVM.

    Unser Angebot

    • You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions.
    • The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges.
    • You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.

    Themen mit denen du dich im Job beschäftigst

    Job Standorte

    • Standort München

      Bayern

      Deutschland

    Das ist dein Arbeitgeber

    Synopsys

    Synopsys

    Synopsys Inc. ist ein führender Softwarehersteller. Die Gesellschaft produziert EDA-Software (electronic design automation) für die Elektronikindustrie.

    Description

  • Unternehmenstyp
    Etablierte Firma
  • Arbeitsmodell
    Hybrid, Onsite
  • Branche
    Internet, IT, Telekom
  • Logo Synopsys

    ASIC Digital Design Verification Principal Engineer

    Ort
    München
    Arbeitsmodell
    Onsite
    Diversität
    Für alle Personen geeignet (m/w/d)
    Nur Englisch
    Nur Englisch erforderlich

    Weitere Jobs